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dual hdmi receiver, multiformat hdtv video decoder, and rgb graphics digitizer ad9388a rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007C2010 analog devices, inc. all rights reserved. features dual hdmi 1.3 receiver hdmi support deep c olor support xvycc e nhanced colorimetry gamut metadata 225 mhz hdmi receiver repeater support high-bandwidth digital content protection (hdcp 1.3) s/pdif (iec60958-compatible) digital audio output multichannel i2s audio output (up to 8 channels) adaptive equalizer for cable lengths up to 30 meters internal edid ram dvi 1.0 multiformat decoder three 10-bit analog-to-digital converters (adcs) adc sampling rates up to 170 mhz mux with 12 analog input channels 525i-/625i-component sd support 525p-/625p-component progressive scan support 720p-/1080i-/1080p-component hdtv support digitizes rgb graphics up to 1600 1200 at 60 hz (uxga) vbi data slicer (including teletext) analog-to-hdmi fast switching general highly flexible output interface stdi function support standard identification 2 any-to-any, 3 3 color-space conversion matrices programmable interrupt request output pins applications advanced tvs pdp hdtvs lcd tvs (hdtv ready) lcd/dlp? rear projection hdtvs crt hdtvs lcos? hdtvs audio/video receivers (avrs) lcd/dlp front projectors hdtv stbs with pvr dvd recorders with progressive scan input support general description the ad9388a is a high quality, single-chip graphics digitizer with an integrated 2:1 multiplexed hdmi? receiver. the ad9388a contains one main component processor (cp) that processes yprpb and rgb component formats, including rgb graphics. the cp also processes the video signals from the hdmi receiver. the ad9388a can keep the hdcp link between an hdmi source and the selected hdmi port active in analog mode operation. this allows for fast switching between the analog and hdmi modes. the ad9388a supports the decoding of a component rgb or yprpb video signal into a digital ycrcb or rgb pixel output stream. the support for component video includes 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well as many other hd and smpte standards. graphics digitization is also supported by the ad9388a. the ad9388a is capable of digitizing rgb graphics signals from vga to uxga rates and converting them into a digital rgb or ycrcb pixel output stream. the ad9388a incorporates a dual input hdmi-compatible receiver that supports hdtv formats up to 1080p and display resolutions up to uxga (1600 1200 at 60 hz). the reception of encrypted video is possible with the inclusion of hdcp. in addition, the inclusion of adaptive equalization ensures robust operation of the interface with cable lengths up to 30 meters. the hdmi receiver has advanced audio functionality, such as a mute controller that prevents audible extraneous noise in the audio output. derivative parts of the ad9388a are available; ad9388abstz-a5 is composed of one analog and one digital input. to facilitate pro- fessional applications, where hdcp processing and decryption are not required, the ad9388abstz-5p derivative is available. this allows users who are not hdcp adopters to purchase the ad9388a (see the ordering guide section for details on these derivative parts). fabricated in an advanced cmos process, the ad9388a is available in a space-saving, 144-lead, surface-mount, rohs- compliant, plastic lqfp and is specified over the ?40c to +85c temperature range.
ad9388a rev. f | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications..................................................................................... 4 electrical characteristics............................................................. 4 analog and hdmi specifications .............................................. 6 data and i 2 c timing characteristics......................................... 7 absolute maximum ratings............................................................ 9 thermal resistance ...................................................................... 9 package thermal performance................................................... 9 esd caution.................................................................................. 9 pin configurations and function descriptions ......................... 10 functional overview...................................................................... 16 analog front end ....................................................................... 16 hdmi receiver........................................................................... 16 component processor pixel data output modes.................. 16 component video processing .................................................. 16 rgb graphics processing ......................................................... 16 general features......................................................................... 16 theory of operation ...................................................................... 17 analog front end....................................................................... 17 hdmi receiver........................................................................... 17 component processor (cp)...................................................... 17 vbi data processor.................................................................... 17 pixel output formatting................................................................ 18 register map architecture ........................................................ 20 typical connection diagram ................................................... 21 recommended external loop filter components................ 22 ad9388a evaluation platform..................................................... 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 10/10rev. e to rev. f added hdmi registered trademark ............................................ 1 changes to features section............................................................ 1 changes to ordering guide .......................................................... 24 added hdmi paragraph ............................................................... 24 8/09rev. d to rev. e changes to pin no. order for ain1 to ain12 pins (table 6) ........10 changes to ordering guide...................................................................24 4/09rev. c to rev. d changes to package thermal performance section .................... 9 changes to vbi data processor section...................................... 17 1/09rev. b to rev. c changes to static performance parameter and power requirements parameter, table 1 .................................. 4 changes to hdmi specifications parameter, table 2.................. 6 change to maximum junction temperature (t j_max ), table 4 ......... 9 changes to package thermal performance section .................... 9 change to figure 6 ......................................................................... 13 changes to ad9388a evaluation platform section .................. 23 changes to table 13........................................................................ 23 changes to figure 11...................................................................... 23 changes to ordering guide .......................................................... 24 7/08revision b: initial version
ad9388a rev. f | page 3 of 24 functional block diagram 06915-001 sync extract sync source and polarity detect standard identification av code insertion macrovision and cgms detection offset adder gain control digital fine clamp prog. delay active peak and hsync depth noise and calibration data preprocessor color-space converter decimation and downsampling filters component processor digital processing block analog interface (a) (b) (c) (a) (b) (c) embedded sync mux xor packet processor hdcp eeprom hdcp engine data recovery alignment hdmi decode 4:2:2 to 4:4:4 conversion mux pll sampler equalizer mux sampler equalizer edid/ repeater controller rxa_0 rxa_1 rxa_2 rxb_0 rxb_1 rxa_c rxb_c rxb_2 audio processing packet/ infoframe memory ddca_scl ddca_sd a ddcb_sd a ddcb_scl 10 10 10 adc0 adc1 adc2 input matrix rgb yprpb clamp clamp clamp llc generation sync processing and clock generation sog soy hs_in/cs_in vs_in scl sda alsb control interface i 2 c hs/cs, vs control control and data control output formatter 10 p0 to p9 10 p10 to p19 10 p20 to p29 int1 hs/cs vs/field de/field llc sync_out/ int2 filter ad9388a de vs hs pixel data i 2 s lrclk sclk mclkout spdif vbi decoder ancillary data formatter ancillary data vbi data processor mda mcl figure 1.
ad9388a rev. f | page 4 of 24 specifications electrical characteristics avdd = 1.71 v to 1.89 v, dvdd = 1.62 v to 1.98 v, dvddio = 2.97 v to 3.63 v, pvdd = 1.71 v to 1.89 v, tvdd = 3.135 v to 3.465 v, cvdd = 1.71 v to 1.89 v. operating temperature range is ?40c to +85c, unless otherwise noted. table 1. parameter 0 f 1 symbol test conditions min typ max unit static performance 1 f 2 resolution (each adc) n 10 bits integral nonlinearity inl bsl at 27 mhz (@ a 10-bit level) C0.5/+2 lsb bsl at 54 mhz (@ a 10-bit level) C0.5/+2 lsb bsl at 74 mhz (@ a 10-bit level) C0.5/+1.5 lsb bsl at 110 mhz (@ a 10-bit level) C0.7/+2 lsb bsl at 170 mhz (@ an 8-bit level) C0.25/+0.5 lsb differential nonlinearity dnl at 27 mhz (@ a 10-bit level) C0.5/+0.5 lsb at 54 mhz (@ a 10-bit level) 0.5 lsb at 74 mhz (@ a 10-bit level) 0.5 lsb at 110 mhz (@ a 10-bit level) 0.5 lsb at 170 mhz (@ an 8-bit level) C0.25/+0.2 lsb digital inputs input high voltage 2 f 3 v ih 2 v hs_in, vs_in low trigger mode 0.7 v input low voltage 3 v il 0.8 v hs_in, vs_in low trigger mode 0.3 v input current i in pin 21 ( a a a reset e e e aaa ) C60 +60 a all input pins other than pin 21 C10 +10 a input capacitance 3 f 4 c in 10 pf digital outputs output high voltage 4 f 5 v oh i source = 0.4 ma 2.4 v output low voltage 5 v ol i sink = 3.2 ma 0.4 v high impedance leakage current i leak 10 a output capacitance 4 c out 20 pf power requirements 4 digital core power supply dvdd 1.62 1.8 1.98 v digital i/o power supply dvddio 2.97 3.3 3.63 v pll power supply pvdd 1.71 1.8 1.89 v analog power supply avdd 1.71 1.8 1.89 v terminator power supply tvdd 3.135 3.3 3.465 v comparator power supply cvdd 1.71 1.8 1.89 v digital core supply current i dvdd graphics rgb sampling @ 108 mhz 5 f 6, 7 141 290 ma yprpb 1080p sampling @ 148.5 mhz 6, 7 203 305 ma hdmi rgb sampling @ 165 mhz 7, 7 f 8, 8 f 9 242 358 ma hdmi rgb sampling @ 225 mhz 7, 8, 9 242 414 ma digital i/o supply current i dvddio graphics rgb sampling @ 108 mhz 6, 7 17 80 ma yprpb 1080p sampling @ 148.5 mhz 6, 7 42 136 ma hdmi rgb sampling @ 165 mhz 7, 8, 9 17 192 ma hdmi rgb sampling @ 225 mhz 7, 8, 9 20 151 ma hdmi comparators i cvdd graphics rgb sampling @ 108 mhz 6, 7 56 83 ma
ad9388a rev. f | page 5 of 24 parameter 0 f 1 symbol test conditions min typ max unit tmds pll and equalizer supply current yprpb 1080p sampling @ 148.5 mhz 6, 7 56 83 ma hdmi rgb sampling @ 165 mhz 7, 8, 9 86 111 ma hdmi rgb sampling @ 225 mhz 7, 8, 9 95 125 ma analog supply current i avdd graphics rgb sampling @ 108 mhz 6, 7 174 312 ma yprpb 1080p sampling @ 148.5 mhz 6, 7 180 318 ma hdmi rgb sampling @ 165 mhz 7, 8, 9 0 2 ma hdmi rgb sampling @ 225 mhz 7, 8, 9 0 2 ma terminator supply current i tvdd graphics rgb sampling @ 108 mhz 6, 7 12 20 ma yprpb 1080p sampling @ 148.5 mhz 6, 7 12 20 ma hdmi rgb sampling @ 165 mhz 7, 8, 9, 9 f 10 42 97 ma hdmi rgb sampling @ 225 mhz 7, 8, 9, 10 63 100 ma audio and video supply current i pvdd graphics rgb sampling @ 108 mhz 6, 7 14 22 ma yprpb 1080p sampling @ 148.5 mhz 6, 7 19 25 ma hdmi rgb sampling @ 165 mhz 7, 8, 9 10 20 ma hdmi rgb sampling @ 225 mhz 7, 8, 9 15 21 ma power-down current i pwrdn 11.6 ma power-up time t pwrup 25 ms 1 the minimum/maximum specifications are guaranteed over the ?40c to +85c temperature range (t min to t max ). 2 all adc linearity tests performed at input range of full scale ? 12.5% and at zero scale + 12.5%. 3 pin 1, pin 105, pin 106, and pin 144 are 5 v tolerant. 4 guaranteed by characterization. 5 v oh and v ol levels obtained using default drive strength value (0x15) in user map register 0xf4. 6 current measurements for analog inputs were made with hdmi/analog simultaneous mode disabled (user map register 0xba, bit 7, p rogrammed with value 0) and no hdmi sources connected to the part. 7 typical current measurements were taken wi th nominal voltage supply leve ls and an smpte bar video pattern input. maximum curre nt measurements were taken with maximum rating voltage supply levels and a moirx video pattern input. 8 current measurements for hdmi inputs were made with a source conne cted to the active hdmi port and no source connected to the inactive hdmi port. 9 audio stream is an uncompressed stereo audio sampling frequency of f s = 48 khz and mclkout = 256 f s . 10 the terminator supply current may vary with the hdmi source in use.
ad9388a rev. f | page 6 of 24 analog and hdmi specifications avdd = 1.71 v to 1.89 v, dvdd = 1.62 v to 1.98 v, dvddio = 2.97 v to 3.63 v, pvdd = 1.71 v to 1.89 v, tvdd = 3.135 v to 3.465 v, cvdd = 1.71 v to 1.89 v. operating temperature range is ?40c to +85c, unless otherwise noted. table 2. parameter 1 0 f 1, 2 test conditions min typ max unit analog clamp circuitry external clamp capacitor 0.1 f input impedance (except pin 74) clamps switched off 10 m input impedance of pin 74 20 k cml 0.88 v adc full-scale level cml + 0.5 v adc zero-scale level cml ? 0.5 v adc dynamic range 1 v clamp level (when locked) component input (y signal) cml ? 0.120 v component input (pr signal) cml v component input (pb signal) cml v pc rgb input (r, g, b signals) cml ? 0.120 v hdmi specifications 1 2 f 3 intrapair (positive-to-negative) differential input skew 1 3 f 4, 1 4 f 5 0.4 t bit channel-to-channel differential input skew 5, 1 5 f 6 0.2 t pixel + 1.78 ns 1 the minimum/maximum specifications are guaranteed over the ?40c to +85c temperature range. 2 guaranteed by characterization. 3 guaranteed by design. 4 t bit is 1/10 the pixel period of the tmds clock. 5 the unit of measurement depe nds on the video applied and the tmds clock frequency. 6 t pixel is the period of the tmds clock.
ad9388a rev. f | page 7 of 24 data and i 2 c timing characteristics avdd = 1.71 v to 1.89 v, dvdd = 1.62 v to 1.98 v, dvddio = 2.97 v to 3.63 v, pvdd = 1.71 v to 1.89 v, tvdd = 3.135 v to 3.465 v, cvdd = 1.71 v to 1.89 v. operating temperature range is ?40c to +85c, unless otherwise noted. table 3. parameter 1 6 f 1, 1 2 symbol test conditions min typ max unit system clock and crystal crystal nominal frequency 28.6363 mhz crystal frequency stability 50 ppm horizontal sync input frequency 14.8 110 khz llc frequency range 12.825 170 mhz i 2 c ports (fast mode) 1 8 f 3 xcl frequency 1 9 f 4 400 khz xcl minimum pulse width high 4 t 1 0.6 s xcl minimum pulse width low 4 t 2 1.3 s hold time (start condition) t 3 0.6 s setup time (start condition) t 4 0.6 s xda setup time 4 t 5 100 ns xcl and xda rise times 4 t 6 300 ns xcl and xda fall times 4 t 7 300 ns setup time (stop condition) t 8 0.6 s i 2 c ports (normal mode) xcl frequency 4 100 khz xcl minimum pulse width high 4 t 1 4 s xcl minimum pulse width low 4 t 2 4.7 s hold time (start condition) t 3 4 s setup time (start condition) t 4 4.7 s xda setup time 4 t 5 250 ns xcl and xda rise times 4 t 6 1000 ns xcl and xda fall times 4 t 7 300 ns setup time (stop condition) t 8 4 s reset feature reset pulse width 5 ms clock outputs llc mark-space ratio t 9 :t 10 45:55 55:45 % duty cycle data and control outputs data output transition time sdr (cp) 2 0 f 5 t 11 end of valid data to negative clock edge 2 ns t 12 negative clock edge to start of valid data 0.5 ns i 2 s port (master mode) sclk mark-space ratio t 13 :t 14 45:55 55:45 % duty cycle lrclk data transition time t 15 end of valid data to negative sclk edge 10 ns lrclk data transition time t 16 negative sclk edge to start of valid data 10 ns i2sx data transition time 2 1 f 6 t 17 end of valid data to negative sclk edge 5 ns i2sx data transition time 6 t 18 negative sclk edge to start of valid data 5 ns mclkout frequency 4.096 24.576 mhz 1 the minimum/maximum specifications are guaranteed over the ?40c to +85c temperature range (t min to t max ). 2 guaranteed by characterization. 3 refers to all i 2 c pins (ddc and control port). 4 the prefix x refers to pin names beginning with s, ddca_s, and ddcb_s. 5 cp timing figures were obt ained using the maximum drive strength valu e (0x3f) in user map register 0xf4. 6 the suffix x refers to pin names ending with 0, 1, 2, and 3.
ad9388a rev. f | page 8 of 24 timing diagrams xda xcl t 3 t 5 t 6 t 1 t 2 t 7 t 8 t 3 t 4 06915-002 notes 1. the prefix x refers to pin names beginning with s, ddca_s, and ddcb_s. figure 2. i 2 c timing t 9 llc p0 to p29, vs, hs, de/field t 11 t 12 t 10 06915-004 figure 3. pixel port and control cp output timing (cp core) sclk lrclk i2sx left-justified mode i2sx right-justified mode i2sx i 2 s mode msb msb ? 1 t 13 t 14 t 15 t 17 t 18 t 16 msb msb ? 1 lsb msb t 17 t 18 t 17 t 18 notes 1. the suffix x refers to pin names ending with 0, 1, 2, and 3. 06915-005 figure 4. i 2 s timing
ad9388a rev. f | page 9 of 24 absolute maximum ratings package thermal performance table 4. to reduce power consumption during ad9388a operation, turn off unused adcs. parameter rating avdd to agnd 2.2 v dvdd to dgnd 2.2 v pvdd to pgnd 2.2 v dvddio to dgnd 4 v cvdd to cgnd 2.2 v tvdd to tgnd 4 v dvddio to avdd ?0.3 v to +3.6 v dvddio to tvdd ?3.6 v to +3.6 v dvddio to dvdd ?2 v to +2 v cvdd to dvdd ?2 v to +0.3 v pvdd to dvdd ?2 v to +0.3 v avdd to cvdd ?2 v to +2 v avdd to pvdd ?2 v to +2 v avdd to dvdd ?2 v to +2 v avdd to tvdd ?3.6 v to +0.3 v tvdd to dvdd ?2 v to +2 v digital inputs voltage to dgnd dgnd ? 0.3 v to dvddio + 0.3 v digital outputs voltage to dgnd dgnd ? 0.3 v to dvddio + 0.3 v analog inputs voltage to agnd agnd ? 0.3 v to avdd + 0.3 v maximum junction temperature (t j _ max ) 119c storage temperature range ?65c to +150c infrared reflow, soldering (20 sec) 260c on a 4-layer pcb that includes a solid ground plane, the ja value is 25.3c/w. however, due to variations within the pcb metal and, therefore, variations in pcb heat conductivity, the value of ja may differ for various pcbs. the most efficient measurement technique is to use the surface temperature of the package to estimate the die temperature because it is not affected by the variance associated with the ja value. the maximum junction temperature (t j _ max ) of 119c must not be exceeded. the following equation calculates the junction temperature using the measured surface temperature of the package and applies only when no heat sink is used on the device under test: t j _ max = t s + ( jt w total ) where: t s is the surface temperature of the package expressed in degrees celsius. jt is the junction-to-package surface thermal resistance. w total = {( av d d i av d d ) + ( dvdd i dvdd ) + ( dvddio i dvddio ) + ( pvdd i pvdd ) + ( cvdd i cvdd ) + ( tvdd i tvdd )} the ad9388a can be operated in ambient temperatures up to +85c. however, in video modes where highest power is consumed and there is higher than nominal power supply voltages and worst- case video data, operation at these ambient temperatures may cause the junction temperature to exceed its maximum allowed value (119c). one way to avoid this is to restrict the ambient temperature to be below +79c. however, even if the ambient temperature is kept below +79c, the user still needs to observe the thermally efficient pcb design recommendations outlined in this section to ensure that the maximum allowed junction temperature is not exceeded in any video mode. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. contact an analog devices, inc., representative or field appli- cations engineer (fae) for more details on package thermal performance. thermal resistance table 5. package type jt 1 unit 144-lead lqfp (st-144) 1.62 c/w esd caution 1 junction-to-package surface thermal resistance.
ad9388a rev. f | page 10 of 24 pin configurations and function descriptions pin 1 1 ddcb_sda 2 spdif 3 i2s0 4 i2s1 5 i2s2 6 i2s3 7 lrclk 8 sclk 9 mclkout 10 ext_clamp 11 sda 12 scl 13 alsb 14 dgnd 15 dvddio 16 de/field 17 hs/cs 18 vs/field 19 int1 20 sync_out/int2 21 reset 22 dgnd 23 dvdd 24 p0 25 p1 26 p2 27 p3 28 p4 29 p5 30 p6 31 p7 32 p8 33 p9 34 dgnd 35 dvddio 36 p10 73 test0 74 test1 75 sog 76 ain7 77 ain1 78 ain8 79 ain2 80 ain9 81 ain3 82 agnd 83 agnd 84 avdd 85 refout 86 cml 87 agnd 88 avdd 89 test2 90 refn 91 test3 92 refp 93 ain10 94 ain4 95 ain11 96 ain5 97 soy 98 ain12 99 ain6 100 pgnd 101 pvdd 102 audio_elpf 103 cgnd 104 cvdd 105 ddca_scl 106 ddca_sda 107 test4 108 test5 109 cvdd 110 cgnd 111 tvdd 112 rxa_cn 113 rxa_cp 114 tgnd 115 rxa_0n 116 rxa_0p 117 tgnd 118 rxa_1n 119 rxa_1p 120 tgnd 121 rxa_2n 122 rxa_2p 123 tvdd 124 rterm 125 cvdd 126 cgnd 127 tvdd 128 rxb_cn 129 rxb_cp 130 tgnd 131 rxb_0n 132 rxb_0p 133 tgnd 134 rxb_1n 135 rxb_1p 136 tgnd 137 rxb_2n 138 rxb_2p 139 tvdd 140 cgnd 141 cvdd 142 dvdd 143 dgnd 144 ddcb_scl 37 p11 38 p12 39 p13 40 p14 41 p15 42 p16 43 p17 44 p18 45 p19 46 p20 47 p21 48 ext_clk 49 dgnd 50 dvddio 51 llc 52 p22 53 p23 54 p24 55 p25 56 dgnd 57 dvdd 58 p26 59 p27 60 p28 61 p29 62 vs_in 63 hs_in/cs_in 64 dgnd 65 xtal1 66 xtal 67 dvddio 68 pvdd 69 pgnd 70 elpf 71 pvdd 72 pgnd ad9388a top view (not to scale) 06915-006 figure 5. ad9388abstz-170, AD9388ABSTZ-110, and ad9388abstz-5p pin configuration table 6. pin function descriptions pin no. mnemonic type 1 description 14, 22, 34, 49, 56, 64, 143 dgnd g digital ground. 82, 83, 87 agnd g analog ground. 69, 72, 100 pgnd g pll ground. 103, 110, 126, 140 cgnd g comparator ground. 114, 117, 120, 130, 133, 136 tgnd g terminator ground. 15, 35, 50, 67 dvddio p digital i/o supply voltage (3.3 v). 23, 57, 142 dvdd p digital core supply voltage (1.8 v). 84, 88 avdd p analog supply voltage (1.8 v). 68, 71, 101 pvdd p audio and video pll supply voltage (1.8 v). 104, 109, 125, 141 cvdd p hdmi comparator, tmds pll, and equalizer supply voltage (1.8 v). 111, 123, 127, 139 tvdd p terminator supply voltage (3.3 v). 73, 74, 91, 108 test0, test1, test3, test5 i test pins. do not connect. 89 test2 o test pin. do not connect. 107 test4 i/o test pin. do not connect. 77, 79, 81, 94, 96, 99, 76, 78, 80, 93, 95, 98 ain1 to ain12 i analog video input channels.
ad9388a rev. f | page 11 of 24 pin no. mnemonic type 1 description 24 to 33, 36 to 47, 52 to 55, 58 to 61 p0 to p29 o video pixel output port. 19 int1 o interrupt. can be active low or active high. the set of events that triggers an interrupt is under user control. 20 sync_out/int2 o sliced synchroniz ation output signal (sync_out). interrupt signal (int2). 17 hs/cs o horizontal synchronization output signal (hs). composite synchronization (cs). a single signal containing both horizontal and vertical synchronization pulses. 18 vs/field o vertical synchronization output signal (vs). field synchronization (field). fiel d synchronization output signal in all interlaced video modes. 16 de/field o data enable signal (de). indicates active pixel data. field synchronization (field). fiel d synchronization output signal in all interlaced video modes. 11 sda i/o i 2 c port serial data input/output. sda is the data line for the control port. 12 scl i i 2 c port serial clock input. (maximum clock rate of 400 khz.) scl is the clock line for the control port. 13 alsb i this pin sets the second lsb of each ad9388a register map. 21 reset i system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the ad9388a circuitry. 51 llc o line-locked output clock for pixel data. range is 13.5 mhz to 170 mhz. 65 xtal1 o this pin should be connected to the 28.63636 mhz crystal or left as a no connect if an external 3.3 v, 28.63636 mhz clock oscillator source is used to clock the ad9388a. in crystal mode, the crystal must be a fundamental crystal. 66 xtal i input pin for the 28.63636 mhz crystal. this pin can be overdriven by an external 3.3 v, 28.63636 mhz clock oscillator source to clock the ad9388a. 70 elpf o the recommended external loop filter must be connected to this elpf pin. 102 audio_elpf o the recommended external loop filter must be connected to this audio_elpf pin. 85 refout o internal voltage reference output. 86 cml o common-mode level for the internal adcs. 90 refn i internal voltage output. 92 refp i internal voltage output. 63 hs_in/cs_in i hs input signal. used in analog mode for 5-wire timing mode. cs input signal. used in analog mode for 4-wire timing mode. for optimal performance, a 100 series resistor is recommended on the hs_in/cs_in pin. 62 vs_in i vs input signal. this pin is used in analog mode for 5-wire timing mode. for optimal performance, a 100 series resistor is recommended on the vs_in pin. 75 sog i synchronization-on-green input. this pin is used in embedded synchronization mode. 97 soy i synchronization-on-luma input. this pin is used in embedded synchronization mode. 112 rxa_cn i digital input clock complement of port a in the hdmi interface. 113 rxa_cp i digital input clock true of port a in the hdmi interface. 115 rxa_0n i digital input channel 0 complement of port a in the hdmi interface. 116 rxa_0p i digital input channel 0 true of port a in the hdmi interface. 118 rxa_1n i digital input channel 1 complement of port a in the hdmi interface. 119 rxa_1p i digital input channel 1 true of port a in the hdmi interface.
ad9388a rev. f | page 12 of 24 pin no. mnemonic type 1 description 121 rxa_2n i digital input channel 2 complement of port a in the hdmi interface. 122 rxa_2p i digital input channel 2 true of port a in the hdmi interface. 128 rxb_cn i digital input clock complement of port b in the hdmi interface. 129 rxb_cp i digital input clock true of port b in the hdmi interface. 131 rxb_0n i digital input channel 0 complement of port b in the hdmi interface. 132 rxb_0p i digital input channel 0 true of port b in the hdmi interface. 134 rxb_1n i digital input channel 1 complement of port b in the hdmi interface. 135 rxb_1p i digital input channel 1 true of port b in the hdmi interface. 137 rxb_2n i digital input channel 2 complement of port b in the hdmi interface. 138 rxb_2p i digital input channel 2 true of port b in the hdmi interface. 106 ddca_sda i/o hdcp slave serial data port a. 1 ddcb_sda i/o hdcp slave serial data port b. 105 ddca_scl i hdcp slave serial clock port a. 144 ddcb_scl i hdcp slave serial clock port b. 2 spdif o spdif digital audio output. 3 i2s0 o i 2 s audio for channel 1 and channel 2. 4 i2s1 o i 2 s audio for channel 3 and channel 4. 5 i2s2 o i 2 s audio for channel 5 and channel 6. 6 i2s3 o i 2 s audio for channel 7 and channel 8. 7 lrclk o data output clock for left and right audio channels. 8 sclk o audio serial clock output. 9 mclkout o audio master clock output. 10 ext_clamp i external clamp signal. this is an optional mode of operation for the ad9388a. 48 ext_clk i clock input for external clock and clamp mode. this is an optional mode of operation for the ad9388a. 124 rterm i sets internal termination resistance. connect this pin to tgnd using a 500 resistor. 1 g = ground, p = power, i = input, and o = output.
ad9388a rev. f | page 13 of 24 pin 1 1 test6 2 spdif 3 i2s0 4 i2s1 5 i2s2 6 i2s3 7 lrclk 8 sclk 9 mclkout 10 ext_clamp 11 sda 12 scl 13 alsb 14 dgnd 15 dvddio 16 de/field 17 hs/cs 18 vs/field 19 int1 20 sync_out/int2 21 reset 22 dgnd 23 dvdd 24 p0 25 p1 26 p2 27 p3 28 p4 29 p5 30 p6 31 p7 32 p8 33 p9 34 dgnd 35 dvddio 36 p10 73 test0 74 test1 75 sog 76 test24 77 ain1 78 test23 79 ain2 80 test22 81 ain3 82 agnd 83 agnd 84 avdd 85 refout 86 cml 87 agnd 88 avdd 89 test2 90 refn 91 test3 92 refp 93 test21 94 test20 95 test19 96 test18 97 soy 98 test17 99 test16 100 pgnd 101 pvdd 102 audio_elpf 103 cgnd 104 cvdd 105 ddca_scl 106 ddca_sda 107 test4 108 test5 109 cvdd 110 cgnd 111 tvdd 112 rxa_cn 113 rxa_cp 114 tgnd 115 rxa_0n 116 rxa_0p 117 tgnd 118 rxa_1n 119 rxa_1p 120 tgnd 121 rxa_2n 122 rxa_2p 123 tvdd 124 rterm 125 cvdd 126 cgnd 127 tvdd 128 test15 129 test14 130 tgnd 131 test13 132 test12 133 tgnd 134 test11 135 test10 136 tgnd 137 test9 138 test8 139 tvdd 140 cgnd 141 cvdd 142 dvdd 143 dgnd 144 test7 37 p11 38 p12 39 p13 40 p14 41 p15 42 p16 43 p17 44 p18 45 p19 46 p20 47 p21 48 ext_clk 49 dgnd 50 dvddio 51 llc 52 p22 53 p23 54 p24 55 p25 56 dgnd 57 dvdd 58 p26 59 p27 60 p28 61 p29 62 vs_in 63 hs_in/cs_in 64 dgnd 65 xtal1 66 xtal 67 dvddio 68 pvdd 69 pgnd 70 elpf 71 pvdd 72 pgnd ad9388abstz-a5 top view (not to scale) 0 6915-100 figure 6. ad9388abstz- a5 pin configuration table 7. pin function descriptions pin no. mnemonic type 1 description 14, 22, 34, 49, 56, 64, 143 dgnd g digital ground. 82, 83, 87 agnd g analog ground. 69, 72, 100 pgnd g pll ground. 103, 110, 126, 140 cgnd g comparator ground. 114, 117, 120, 130, 133, 136 tgnd g terminator ground. 15, 35, 50, 67 dvddio p digital i/o supply voltage (3.3 v). 23, 57, 142 dvdd p digital core supply voltage (1.8 v). 84, 88 avdd p analog supply voltage (1.8 v). 68, 71, 101 pvdd p audio and video pll supply voltage (1.8 v). 104, 109, 125, 141 cvdd p hdmi comparator, tmds pll, and equalizer supply voltage (1.8 v). 111, 123, 127, 139 tvdd p terminator supply voltage (3.3 v). 128, 129, 131, 132, 134, 135, 137, 138, 108, 91, 74, 73 test15 to test8, test5, test3, test1, test0 i test pins. do not connect. 76, 78, 80, 93 to 96, 98, 99 test24 to test16 i test pins. connec t to agnd through a 10 k resistor. 89 test2 o test pin. do not connect. 107 test4 i/o test pin. do not connect. 77, 79, 81 ain1 to ain3 i analog video input channels.
ad9388a rev. f | page 14 of 24 pin no. mnemonic type 1 description 24 to 33, 36 to 47, 52 to 55, 58 to 61 p0 to p29 o video pixel output port. 19 int1 o interrupt. can be active low or active hi gh. the set of events that triggers an interrupt is under user control. 20 sync_out/int2 o sliced synchroniz ation output signal (sync_out). interrupt signal (int2). 17 hs/cs o horizontal synchronization output signal (hs). composite synchronization (cs). a single signal containing both horizontal and vertical synchronization pulses. 18 vs/field o vertical synchronization output signal (vs). field synchronization (field). field synchronization output signal in all interlaced video modes. 16 de/field o data enable signal (de). indicates active pixel data. field synchronization (field). field synchronization output signal in all interlaced video modes. 11 sda i/o i 2 c port serial data input/output. sda is the data line for the control port. 12 scl i i 2 c port serial clock input. (maximum clock rate of 400 khz.) scl is the clock line for the control port. 13 alsb i this pin sets the second lsb of each ad9388a register map. 21 reset i system reset input. active low. a minimum low reset pulse width of 5 ms is required to reset the ad9388a circuitry. 51 llc o line-locked output clock for pixel data. range is 13.5 mhz to 170 mhz. 65 xtal1 o this pin should be connected to the 28.63636 mhz crystal or left as a no connect if an external 3.3 v, 28.63636 mhz clock oscillator source is used to clock the ad9388a. in crystal mode, the crystal must be a fundamental crystal. 66 xtal i input pin for the 28.63636 mhz crystal. this pin can be overdriven by an external 3.3 v, 28.63636 mhz clock oscillator source to clock the ad9388a. 70 elpf o the recommended external loop filter must be connected to this elpf pin. 102 audio_elpf o the recommended external l oop filter must be connected to audio_elpf. 85 refout o internal voltage reference output. 86 cml o common-mode level for the internal adcs. 90 refn i internal voltage output. 92 refp i internal voltage output. 63 hs_in/cs_in i hs input signal. used in analog mode for 5-wire timing mode. cs input signal. used in analog mode for 4-wire timing mode. for optimal performance, a 100 series resistor is recommended on the hs_in/cs_in pin. 62 vs_in i vs input signal. this pin is used in analog mode for 5-wire timing mode. for optimal performance, a 100 series resist or is recommended on the vs_in pin. 75 sog i synchronization-on-green input. this pin is used in embedded synchronization mode. 97 soy i synchronization-on-luma input. this pin is used in embedded synchronization mode. 112 rxa_cn i digital input clock complement of port a in the hdmi interface. 113 rxa_cp i digital input clock true of port a in the hdmi interface. 115 rxa_0n i digital input channel 0 complement of port a in the hdmi interface. 116 rxa_0p i digital input channel 0 true of port a in the hdmi interface. 118 rxa_1n i digital input channel 1 complement of port a in the hdmi interface. 119 rxa_1p i digital input channel 1 true of port a in the hdmi interface. 121 rxa_2n i digital input channel 2 complement of port a in the hdmi interface. 122 rxa_2p i digital input channel 2 true of port a in the hdmi interface. 106 ddca_sda i/o hdcp slave serial data port a. 1 test6 i/o test pin. do not connect. 105 ddca_scl i hdcp slave serial clock port a. 144 test7 i test pin. connect this pin to dgnd using a 10 k resistor.
ad9388a rev. f | page 15 of 24 pin no. mnemonic type 1 description 2 spdif o spdif digital audio output. 3 i2s0 o i 2 s audio for channel 1 and channel 2. 4 i2s1 o i 2 s audio for channel 3 and channel 4. 5 i2s2 o i 2 s audio for channel 5 and channel 6. 6 i2s3 o i 2 s audio for channel 7 and channel 8. 7 lrclk o data output clock for left and right audio channels. 8 sclk o audio serial clock output. 9 mclkout o audio master clock output. 10 ext_clamp i external clamp signal. this is an optional mode of operation for the ad9388a. 48 ext_clk i clock input for external clock and clamp mode. this is an optional mode of operation for the ad9388a. 124 rterm i sets internal termination resistance. connect this pin to tgnd using a 500 resistor. 1 g = ground, p = power, i = input, and o = output.
ad9388a rev. f | page 16 of 24 functional overview the following overview provides a brief description of the functionality of the ad9388a. more details are available in the theory of operation section. analog front end the analog front end of the ad9388a provides three high quality 10-bit adcs to enable true 10-bi t video decoding, a multiplexer with 12 analog input channels to enable a multisource connection without the requirement of an external multiplexer, and three current and voltage clamp control loops to ensure that dc offsets are removed from the video signal. hdmi receiver the ad9388a is compatible with the hdmi specification. the ad9388a supports all hdtv formats up to 1080p in nonC deep color mode and 1080p in 36-bit deep color mode. furthermore, it supports all display resolutions up to uxga (1600 1200 at 60 hz). this device includes the following features: ? adaptive front-end equalization for hdmi operation over cable lengths of up to 30 meters ? synchronization conditioning for higher performance in strenuous conditions ? audio mute for removing extraneous noises ? programmable data island packet interrupt generator component processor pixel data output modes the ad9388a features single data rate outputs as follows: ? 8-/10-bit 4:2:2 ycrcb for 525i, 625i ? 16-/20-bit 4:2:2 ycrcb for all standards ? 24-/30-bit 4:4:4 ycrcb/rgb for all standards component video processing the ad9388a supports 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other hdtv formats. it provides automatic adjustment of gain (contrast) and offset (brightness), as well as manual adjustment controls. furthermore, the ad9388a not only supports analog component yprpb/rgb video formats with embedded synchronization or with separate hs, vs, and cs, but also supports ycrcb-to-rgb and rgb-to-ycrcb conversions by any-to-any, 3 3 color-space conversion matrices and user- defined pixel sampling for nonstandard video sources. in addition, the ad9388a features brightness, saturation, and hue controls. standard identification (stdi) enables detection of the component format at the system level, and a synchroniza- tion source polarity detector (sspd) determines the source and polarity of the synchronization signals that accompany the input video. certified macrovision? copy protection detection is available on component formats (525i, 625i, 525p, and 625p). when no video input is present, stable timing is provided by the free run output mode. rgb graphics processing the ad9388a provides 170 msps conversion rate support of rgb input resolutions up to 1600 1200 at 60 hz (uxga). the ad9388a offers automatic or manual clamp and gain controls for graphics modes. similar to the component video processing features, the rgb graphics processing for the ad9388a features contrast and brightness controls, automatic detection of synchronization source and polarity by the sspd block, standard identification enabled by the stdi block, and user-defined pixel sampling support for nonstandard video sources. additional rgb graphics processing features of the ad9388a include the following: ? sampling pll clock with 500 ps p-p jitter at 150 msps ? 32-phase dll support of optimum pixel clock sampling ? color-space conversion of rgb to ycrcb and decimation to a 4:2:2 format for videocentric, back-end ic interfacing ? data enable (de) output signal supplied for direct connection to hdmi/dvi transmitter ic general features the ad9388a offers a high quality multiformat video decoder and digitizer that feature hs, vs, and field output signals with programmable position, polarity, and width. it also includes programmable interrupt request output pins (int1 and int2). the part offers low power consumption1.8 v digital core and analog input, and 3.3 v digital input/outputand a low power power-down mode. the ad9388a operates over a temperature range of ?40c to +85c and is available in a 144-lead, 20 mm 20 mm, rohs- compliant lqfp.
ad9388a rev. f | page 17 of 24 theory of operation analog front end the ad9388a analog front end comprises three 10-bit adcs that digitize the analog video signal before applying it to the cp. the analog front end uses differential channels to each adc to ensure high performance in mixed-signal applications. the front end also includes a 12-channel input multiplexer that enables multiple video signals to be applied to the ad9388a. current and voltage clamps are positioned in front of each adc to ensure that the video signal remains within the range of the converter. fine clamping of the video signals is performed downstream by digital fine clamping in the cp. for component 525i, 625i, 525p, and 625p sources, 2 over- sampling is performed, but 4 oversampling is available for component 525i and 625i. all other video standards are 1 oversampled. oversampling the video signals reduces the cost and complexity of external antialiasing (aa) filters, with the additional benefit of increasing the signal-to-noise ratio (snr). hdmi receiver the hdmi receiver on the ad9388a incorporates active equalization of the hdmi data signals. this equalization compensates for the high frequency losses inherent in hdmi and dvi cables, especially those with long lengths and high frequencies. because the ad9338a can provide equalization compensation for cable lengths up to 30 meters, it is capable of achieving robust receiver performance at even the highest hdmi data rates. with the inclusion of hdcp, displays can receive encrypted video content. the hdmi interface of the ad9388a allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the hdcp 1.3 protocol. the hdmi receiver also offers advanced audio functionality. the receiver contains an audio mute controller that can detect a variety of selectable conditions that may result in audible extraneous noise in the audio output. upon detection of these conditions, the audio data can be ramped to prevent audio clicks and pops. component processor (cp) the cp is capable of decoding and digitizing a wide range of component video formats in any color space. component video standards supported by the cp include 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, vga up to uxga at 60 hz, and many other standards. the cp section of the ad9388a contains an agc block. this block is followed by a digital clamp circuit that ensures that the video signal is clamped to the correct blanking level. automatic adjustments within the cp include gain (contrast) and offset (brightness); however, manual adjustment controls are also supported. if no embedded synchronization is present, the video gain can be set manually. a fully programmable, any-to-any, 3 3 color-space converter is placed before the cp section. this enables yprpb-to-rgb and rgb-to-ycrcb conversions. many other standards of color space can be implemented using the color-space converter. a second fully programmable, any-to-any, 3 3 color-space converter is placed in the back end of the cp core. this color- space converter features advanced color controls, such as contrast, saturation, brightness, and hue controls. the output section of the cp can be configured in single data rate (sdr) mode with one data packet per clock cycle. in sdr mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output is possible. in these modes, hs/cs, vs/field, and de/field (where applicable) timing reference signals are provided. the cp section contains circuitry to enable the detection of macrovision-encoded yprpb signals for 525i, 625i, 525p, and 625p. it is designed to be fully robust when decoding these types of signals. vbi data processor vbi extraction of cgms data is performed by the vbi data processor (vdp) section of the ad9388a for interlaced, progressive, and high definition scanning rates. the data extracted is read back over the i 2 c interface. for more detailed product information about the ad9388a, contact a local analog devices sales representative or field applications engineer (fae).
ad9388a rev. f | page 18 of 24 pixel output formatting note that unused pins of the pixel output port are driven with a low voltage. table 8. component processor pixel output pin map (p19 to p0) output of data port pins p[19:0] processor 1 mode format 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cp mode 1 video output 8-bit 4:2:2 2 ycrcb[7:0] cp mode 2 video output 10-bit 4:2:2 2 ycrcb[9:0] cp mode 3 video output 12-bit 4:2:2 2 ycrcb[11:2] cp mode 4 video output 12-bit 4:2:2 2 ycrcb[11:4] cp mode 5 video output 12-bit 4:2:2 2 ycrcb[11:4] ycrcb[3:0] cp mode 6 video output 16-bit 4:2:2 3 , 4 cha[7:0] (default data is y[7:0]) chb/chc[7:0] (default data is cr/cb[7:0]) cp mode 7 video output 20-bit 4:2:2 3 , 4 cha[9:0] (default data is y[9:0]) chb/ chc[9:0] (default data is cr/cb[9:0]) cp mode 8 video output 20-bit 4:2:2 3 , 4 cha[9:2] (default data is y[9:2]) chb/chc[9:2] (default data is cr/cb[9:2]) cp mode 9 video output 24-bit 4:2:2 3 , 4 y[11:2] crcb[11:2] cp mode 10 video output 24-bit 4:2:2 3 , 4 y[11:4] crcb[11:4] cp mode 11 video output 24-bit 4:2:2 3 , 4 y[11:4] y[3:0] crcb[3:0] cp mode 12 video output 24-bit 4:4:4 3 , 4 cha[7:0] (default data is g[7:0] or y[7:0]) chb[7:0] (default data is r[7:0] or cr[7:0]) cp mode 13 video output 24-bit 4:4:4 3 , 4 cha[7:0] (default data is g[7:0] or y[7:0]) chc[7:0] (default data is b[7:0] or cb[7:0]) cp mode 14 video output 24-bit 4:4:4 3 , 4 chc[7:0] (default data is b[7:0] or cb[7:0]) cha[7:0] (default data is g[7:0] or y[7:0]) cp mode 15 video output 24-bit 4:4:4 3 , 4 chc[7:0] (default data is b[7:0] or cb[7:0]) chb[7:0] (default data is r[7:0] or cr[7:0]) cp mode 16 video output 30-bit 4:4:4 3 , 4 cha[9:0] (default data is g[9:0] or y[9:0]) ch b[9:0] (default data is r[9:0] or cr[9:0]) cp mode 17 video output 30-bit 4:4:4 cha[9:0] (default data is g[9:0] or y[9:0]) chc[9:0] (default data is b[9:0] or cb[9:0]) cp mode 18 video output 30-bit 4:4:4 chc[9:0] (default data is b[9:0] or cb[9:0]) cha[9:0] (default data is g[9:0] or y[9:0]) cp mode 19 video output 30-bit 4:2:2 chc[9:0] (default data is b[9:0] or cb[9:0]) ch b[9:0] (default data is r[9:0] or cr[9:0]) 1 the cp processor uses the digitizer or hdmi as input. 2 maximum pixel clock rate of 54 mhz. 3 maximum pixel clock rate of 170 mhz for the analog digitizer. 4 maximum pixel clock ra te of 165 mhz for hdmi.
ad9388a rev. f | page 19 of 24 table 9. component processor pixel output pin map (p29 to p20) output of data port pins p[29:20] processor 1 mode format 29 28 27 26 25 24 23 22 21 20 cp mode 1 video output 8-bit 4:2:2 2 cp mode 2 video output 10-bit 4:2:2 2 cp mode 3 video output 12-bit 4:2:2 2 ycrcb[1:0] cp mode 4 video output 12-bit 4:2:2 2 ycrcb[3:0] cp mode 5 video output 12-bit 4:2:2 2 cp mode 6 video output 16-bit 4:2:2 3 , 4 cp mode 7 video output 20-bit 4:2:2 3 , 4 cp mode 8 video output 20-bit 4:2:2 3 , 4 y[1:0] crcb[1:0] cp mode 9 video output 24-bit 4:2:2 3 , 4 crcb[1:0] y[1:0] cp mode 10 video output 24-bit 4:2:2 3 , 4 crcb[3:0] y[3:0] cp mode 11 video output 24-bit 4:2:2 3 , 4 crcb[11:4] cp mode 12 video output 24-bit 4:4:4 3 , 4 chc[7:0] (for example, b[7:0] or cb[7:0]) cp mode 13 video output 24-bit 4:4:4 3 , 4 chb[7:0] (for example, r[7:0] or cr[7:0]) cp mode 14 video output 24-bit 4:4:4 3 , 4 chb[7:0] (for example, r[7:0] or cr[7:0]) cp mode 15 video output 24-bit 4:4:4 3 , 4 cha[7:0] (for example, g[7:0] or y[7:0]) cp mode 16 video output 30-bit 4:4:4 3 , 4 chc[9:0] (for example, b[9:0] or cb[9:0]) cp mode 17 video output 30-bit 4:4:4 3 , 4 chb[9:0] (for example, r[9:0] or cr[9:0]) cp mode 18 video output 30-bit 4:4:4 3 , 4 chb[9:0] (for example, r[9:0] or cr[9:0]) cp mode 19 video output 30-bit 4:2:2 3 , 4 cha[9:0] (for example, g[9:0] or y[9:0]) 1 the cp processor uses the digitizer or hdmi as input. 2 maximum pixel clock rate of 54 mhz. 3 maximum pixel clock rate of 170 mhz for the analog digitizer. 4 maximum pixel clock ra te of 165 mhz for hdmi.
ad9388a rev. f | page 20 of 24 register map architecture the ad9388a registers are controlled via a 2-wire serial (i 2 c-compatible) interface. the ad9388a has eight maps, each with a unique i 2 c address. the state of the alsb pin (pin 13) sets bit 2 of each register map address in table 10 . table 10. ad9388a map addresses register map address with alsb = low address with alsb = high programmable address location at which address can be programmed user map 0x40 0x42 not programmable n/a user map 1 0x44 0x46 programmable user map 2, register 0xeb user map 2 0x60 0x62 programmable user map, register 0x0e vdp map 0x48 0x4a programmable user map 2, register 0xec reserved map 0x4c 0x4e programmable user map 2, register 0xea hdmi map 0x68 0x6a programmable user map 2, register 0xef repeater/ksv map 0x64 0x66 programmable user map 2, register 0xed edid map 0x6c 0x6e programmable user map 2, register 0xee scl sda sa: programmable sa: programmable sa: programmable sa: programmable sa: programmable sa: programmable sa: programmable reserved map repeater/ ksv map edid map hdmi map sa: 0x40 vdp map user map 2 user map 1 user map 06915-007 figure 7. register map access through the main i 2 c port
ad9388a rev. f | page 21 of 24 typical connection diagram 06915-008 figure 8. typical connection diagram
ad9388a rev. f | page 22 of 24 recommended external lo op filter components note that the external loop filter components for the elpf and audio_elpf pins should be placed as close as possible to the res pective pins. the recommended component values are specified in figure 9 and figure 10 . 1.5k ? 80nf 8nf pvdd = 1.8v a udio_elpf 102 06915-010 1.69k ? 82nf 10nf pvdd = 1.8v elpf 70 06915-009 figure 10. audio_elpf components figure 9. elpf components
ad9388a rev. f | page 23 of 24 ad9388a evaluation platform analog devices has developed an advanced tv (atv) evaluation platform for the ad9388a decoder. the evaluation platform consists of a motherboard and two daughterboards. the mother- board features a xilinx fpga for digital processing and muxing functions. the motherboard also features three ad9742 devices (12-bit dacs) from analog devices. this allows the user to drive a vga monitor with just the motherboard and front-end board. the back end of the platform can be connected to a specially developed video output board from analog devices. this modular board features an analog devices encoder and an analog devices hdmi transmitter. the front end of the platform consists of an ad9388a evaluation board (eval-ad9388afez_x). this board feeds the digital outputs from the decoder to the fpga on the motherboard. the evaluation board comes with one of the pin-compatible decoders listed in table 11 . table 11. front-end modular board details front-end modular board model on-board decoder hdcp license required eval-ad9388afez_1 ad9388abstz-170 yes eval-ad9388afez_2 ad9388abstz-5p no eval-ad9388afez_3 ad9388abstz-a5 yes video input board eval-ad9388afez_x ad9388a decoder analog and digital video inputs atv motherboard video output board xilinx fpga vga output avi 168-pin connector avo 168-pin connector hdmi y/c cvbs yprpb ad9889b adv7341 audio 96-pin connector 06915-101 figure 11. functional block diagram of evaluation platform
ad9388a rev. f | page 24 of 24 outline dimensions compliant to jedec standards ms-026-bfb 051706-a 0.27 0.22 0.17 1 36 37 73 72 108 144 109 top view (pins down) 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 22.20 22.00 sq 21.80 20.20 20.00 sq 19.80 figure 12. 144-lead low profile quad flat package [lqfp] (st-144) dimensions shown in millimeters ordering guide model 1 , 2 , 3 , 4 , 5 temperature range package description package option ad9388abstz-170 C40c to +85c 144-lead low profile quad flat package [lqfp] st-144 AD9388ABSTZ-110 C40c to +85c 144-lead low profile quad flat package [lqfp] st-144 ad9388abstz-5p C40c to +85c 144-lead low profile quad flat package [lqfp] st-144 ad9388abstz-a5 C40c to +85c 144-lead low profile quad flat package [lqfp] st-144 1 z = rohs compliant part. 2 the ad9388abstz-170, AD9388ABSTZ-110, and ad9833abstz-a5 are programme d with internal hdcp keys. customers must have hdcp adop ter status (consult digital content protection, llc, for licensing requirements) to purchase any components with internal hdcp keys. 3 the ad9388abstz-5p speed grade: 5 = 170 mh z; hdcp functionality: p = no hdcp functionality (profe ssional version). 4 the ad9388abstz-5p professional version fo r non-hdcp encrypted applications. user is not required to be an hdcp adopter. 5 the ad9388abstz-a5 speed grade: 5 = 170 mhz; in put configuration: a = 1 analog (ain1, ain2, ain3, hs_in/cs_in, vs_in, sog, and soy), 1 digital (1 hdmi port). i 2 c refers to a communications protocol originally developed by phillips semi conductors (now nxp semiconductors). hdmi, the hdmi logo, and high-definition multimedia interface are trademarks or registered trademarks of hdmi licensing llc in the united states and other countries. ?2007C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06915-0-10/10(f)

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